Field effect transistors (FETs) are the basic building blocks of today's integrated circuits. Such transistors can be formed in conventional substrates (such as a silicon substrate), or in silicon-on-insulator substrates. In both cases one introduces so-called deep implants into the substrate to improve the performance of the transistor, to provide heavy doping isolation for complementary metal-oxide (CMOS) integrated circuits, to reduce the current gain of parasitic vertical transistors, and to reduce the parasitic latch-up effect, just to mention some of the reasons why deep implants are used.
In CMOS technology, these deep implants are referred to as p-well or n-well deep implants. These p-well or n-well deep implants are needed if one forms NMOS-transistors (p-well) and PMOS-transistors (n-well) within one and the same substrate.
In addition to these deep implants, usually also threshold adjust implants (V.sub.T adjust implants) and punch through implants are employed to set the appropriate threshold voltage (V.sub.T) for each transistor and to prevent punch through.
A conventional MOSFET 10 is shown in FIG. 1A. Such a MOSFET is typically formed in a silicon substrate 11 and comprises a doped source region 14 and a doped drain region 12 being arranged to the left and right of a gate conductor 13. This gate conductor 13 is separated from the channel 17--which is situated between the source 14 and drain regions 12--by a date oxide layer 15. STI, LOCOS or poly-buffered LOCOS isolations (not shown) are usually employed to provide for isolation of adjacent transistors.
The dopant concentration as a function of the distance (cut H.sub.PA --H.sub.PA) is illustrated in FIG. 1B. Please note that this representation is schematical and is shown only to illustrate fundamental differences between know MOSFETs and MOSFETs according to the present invention. For the definition of the source and drain regions 12, 14 As implants have been used. The concentration of these dopants is about 1.times.10.sup.21 /cm.sup.3. The interface 18 to the channel 17 is not well defined because of the sloped side walls 16 of the gate pillar 13, i.e. the As concentration decreases as a function of the distance (graded concentration at the interface 18). In a conventional MOSFET, the deep implants (e.g. boron; p-type) and the threshold adjust implants (e.g. indium, p-type) extend across the whole length of the transistor. The deep implants can be made using conventional techniques. These implants are usually made in preparation of the substrate before the actual FETs are formed. The combined concentration of B+In is about 2.times.10.sup.17 /cm.sup.3.
Please note that with conventional processes it is impossible to provide threshold adjust implants and punch through implants which are localized underneath the channel 17 only.
There are currently no FET fabrication schemes known that would allow to realize FETs with threshold adjust implants and/or punch through implants being well defined and located underneath the channel only.
There is background art relating to various aspects of implanting dopants. Two examples are U.S. Pat. No. 4,471,523 and U.S. Pat. No. 5,547,894, both currently assigned to the assignee of the present application.
The present patent application is related to U.S. patent application Ser. No. 09/026,261, entitled "METHOD FOR MAKING FIELD EFFECT TRANSISTORS HAVING SUB-LITHOGRAPHIC GATES WILL VERTICAL SIDE WALLS", and U.S. patent application Ser. No. 09/025,093, entitled "FIELD EFFECT TRANSISTORS WITH VERTICAL GATE SIDE WALLS AND METHOD FOR MAKING SUCH TRANSISTORS", both filed on the same day and presently assigned to the assignee of the instant application. The disclosure of these two patent applications is incorporated herein by reference.
It is an object of the present invention to provide FETs having threshold adjust implants and/or punch through implants being located underneath the channel only.
It is an object of the present invention to provide FETs having threshold adjust implants and/or punch through implants being well defined.
It is another object of the present invention to provide a method for the formation of FETs having threshold adjust implants and/or punch through implants being located underneath the channel only.
It is another object of the present invention to provide a method for the formation of FETs having threshold adjust implants and/or punch through implants being well defined.